SH7144 Datasheet, PDF (28/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Figure 11.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode .................. 263
Figure 11.33 Example of Complementary PWM Mode Setting Procedure................................ 264
Figure 11.34 Complementary PWM Mode Counter Operation.................................................. 266
Figure 11.35 Example of Complementary PWM Mode Operation ............................................ 267
Figure 11.36 Example of PWM Cycle Updating ........................................................................ 269
Figure 11.37 Example of Data Update in Complementary PWM Mode .................................... 271
Figure 11.38 Example of Initial Output in Complementary PWM Mode (1)............................. 272
Figure 11.39 Example of Initial Output in Complementary PWM Mode (2)............................. 273
Figure 11.40 Example of Complementary PWM Mode Waveform Output (1).......................... 274
Figure 11.41 Example of Complementary PWM Mode Waveform Output (2).......................... 275
Figure 11.42 Example of Complementary PWM Mode Waveform Output (3).......................... 275
Figure 11.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) .. 276
Figure 11.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) .. 276
Figure 11.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) .. 277
Figure 11.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) .. 277
Figure 11.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) .. 278
Figure 11.48 Example of Toggle Output Waveform Synchronized with PWM Output............. 279
Figure 11.49 Counter Clearing Synchronized with Another Channel ........................................ 280
Figure 11.50 Example of Output Phase Switching by External Input (1)................................... 281
Figure 11.51 Example of Output Phase Switching by External Input (2)................................... 281
Figure 11.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) .. 282
Figure 11.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) .. 282
Figure 11.54 Count Timing in Internal Clock Operation............................................................ 287
Figure 11.55 Count Timing in External Clock Operation........................................................... 287
Figure 11.56 Count Timing in External Clock Operation (Phase Counting Mode).................... 287
Figure 11.57 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 288
Figure 11.58 Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode).......................... 288
Figure 11.59 Input Capture Input Signal Timing........................................................................ 289
Figure 11.60 Counter Clear Timing (Compare Match) .............................................................. 289
Figure 11.61 Counter Clear Timing (Input Capture) .................................................................. 290
Figure 11.62 Buffer Operation Timing (Compare Match).......................................................... 290
Figure 11.63 Buffer Operation Timing (Input Capture) ............................................................. 290
Figure 11.64 TGI Interrupt Timing (Compare Match) ............................................................... 291
Figure 11.65 TGI Interrupt Timing (Input Capture) ................................................................... 291
Figure 11.66 TCIV Interrupt Setting Timing.............................................................................. 292
Figure 11.67 TCIU Interrupt Setting Timing.............................................................................. 292
Figure 11.68 Timing for Status Flag Clearing by the CPU......................................................... 293
Figure 11.69 Timing for Status Flag Clearing by DTC/DMAC Activation ............................... 293
Figure 11.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 294
Figure 11.71 Contention between TCNT Write and Clear Operations....................................... 295
Figure 11.72 Contention between TCNT Write and Increment Operations ............................... 296
Figure 11.73 Contention between TGR Write and Compare Match........................................... 296
Rev. 2.0, 09/02, page xxvi of xxxviii