SH7144 Datasheet, PDF (769/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Index
A/D conversion time............................... 472
A/D converter ......................................... 463
Activation by interrupt............................ 122
Activation by software............................ 123
Address error exception processing .......... 60
Address map ..................................... 46, 128
Addressing modes..................................... 22
Advanced user debugger (AUD)............. 611
Asynchronous serial communication ...... 381
Auto-request mode.................................. 163
Block configuration ................................ 576
Block transfer mode................................ 118
Boot mode............................................... 582
Branch trace mode .................................. 614
Buffer operation...................................... 242
Burst mode.............................................. 175
Bus arbitration ........................................ 144
Bus masters............................................. 144
Bus release state........................................ 42
Bus state controller (BSC) ...................... 125
Byte data ................................................... 17
Cascaded operation ................................. 245
Chain transfer.......................................... 119
Clock mode............................................... 44
Clock pulse generator ............................... 47
Clocked synchronous communication .... 398
Compare match ....................................... 237
Compare match timer (CMT) ................. 481
Complementary PWM mode .................. 261
Continuous scan mode ............................ 471
Control registers........................................ 15
CPU .......................................................... 13
Crystal oscillator ....................................... 48
Cycle-steal mode..................................... 175
Data format in registers............................. 17
Data formats.............................................. 17
Data formats in memory ........................... 17
Data transfer controller (DTC)................103
Delayed branch instructions ......................19
Direct memory access controller (DMAC)
................................................................ 149
DTC vector addresses .............................113
Dual address mode ..................................170
Effective address .......................................22
Electrical characteristics..........................665
Error Protection.......................................592
Exception processing ................................53
Exception processing state ........................42
Exception processing vector table.............55
External clock input ..................................49
External request mode.............................163
Fixed mode..............................................165
Flash memory..........................................571
Flash memory emulation in RAM...........585
Free-running counters .............................236
Function for detecting the oscillator halt...50
Functions of multiplexed pins .................489
General illegal instructions .......................63
General registers (Rn) ...............................13
Global base register (GBR) .......................16
Hardware protection................................591
Hitachi user debug interface (H-UDI).....599
Hitachi user debug interface (H-UDI)
interrupt ..................................................... 78
I/O ports ..................................................553
I²C bus format .........................................435
I²C bus interface......................................411
Illegal slot instructions ..............................63
Immediate data format ..............................18
Input capture function .............................239
Internal clock.............................................47
Interrupt controller (INTC) .......................67
Rev. 2.0, 09/02, page 729 of 732