SH7144 Datasheet, PDF (115/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

6.3.4 Interrupt Priority Registers A to J (IPRA to IPRJ)
Interrupt priority registers are ten 16-bit readable/writable registers that set priority levels from 0
to 15 for interrupts except NMI. For the correspondence between interrupt request sources and
IPR, refer to table 6.2, Interrupt Exception Processing Vectors and Priorities. Each of the
corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of
the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should
be set H'0 (B’0000.)
Bit
Bit Name Initial Value R/W Description
15
IPR15 0
14
IPR14 0
13
IPR13 0
12
IPR12 0
R/W These bits set priority levels for the corresponding
R/W ^{interrupt source.}
R/W ^{0000: Priority level 0 (lowest)}
0001: Priority level 1
R/W _{0010: Priority level 2}
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
11
IPR11 0
10
IPR10 0
9
IPR9
0
8
IPR8
0
R/W These bits set priority levels for the corresponding
R/W ^{interrupt source.}
R/W ^{0000: Priority level 0 (lowest)}
0001: Priority level 1
R/W _{0010: Priority level 2}
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
Rev. 2.0, 09/02, page 75 of 732