SH7144 Datasheet, PDF (659/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

23.5 Usage Notes
23.5.1 Initialization
The debugger's internal buffers and processing states are initialized in the following cases:
1. In a power-on reset
2. When AUDRST is driven low
3. When the AUDSRST bit in the SYSCR register is cleared to 0 (see section 24.2.2)
4. When the MSTP3 bit in the MSTCR2 register is set to 1 (see section 24.2.3)
23.5.2 Operation in Software Standby Mode
The debugger is not initialized in software standby mode. However, since this LSI's internal
operation halts in software standby mode:
1. When AUDMD is high (RAM monitor mode), Ready is not returned (Not Ready continues to
be returned).
However, when operating on an external clock, the protocol continues.
2. When AUDMD is low (branch trace mode), operation stops. However, operation continues
when software standby is released.
23.5.3 Setting the PA15/CK pin
Some debug tools have specification that the AUDCK signal is generated out of the CK signal.
Decide the pin function controller setting after reading the manual of the debug tool to be used.
23.5.4 Pin States
1. Module standby
AUDMD
Z
AUDCK
Z
AUDSYNC Z
AUDATA Z
2. AUDRST = low-level input
AUDMD
Input
AUDCK
(1) AUDMD = high: Input
AUDSYNC (1) AUDMD = high: Input
AUDRST
Low-level input
AUDATA (1) AUDMD = high: Input
(2) AUDMD = low: High-level Output
(2) AUDMD = low: High-level Output
(2) AUDMD = low: High-level Output
Rev. 2.0, 09/02, page 619 of 732