SH7144 Datasheet, PDF (612/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Internal address bus
Internal data bus (32 bits)
FLMCR1
FLMCR2
EBR1
EBR2
RAMER
Bus interface/controller
Flash memory
(256 kbytes)
Operating
mode
FWP pin
Mode pin
Legend
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR1: Erase block register 1
EBR2: Erase block register 2
RAMER: RAM emulation register
Figure 19.1 Block Diagram of Flash Memory
19.2 Mode Transitions
When the mode pin and the FWP pin are set in the reset state and a reset-start is executed, this LSI
enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not
programmed or erased.
The boot mode, user program mode, and PROM programmer modes are provided as modes to
write and erase the flash memory.
The differences between boot mode and user program mode are shown in table 19.1.
Figure 19.3 shows boot mode, and figure 19.4 shows user program mode.
Rev. 2.0, 09/02, page 572 of 732