SH7144 Datasheet, PDF (469/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

14.3.6 I²C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that includes flags that indicate bus states and a bit for
the checking and control of the acknowledge signal.
Bit
Bit Name
7 ESTP
6 STOP
Initial
Value
0
0
R/W
R/(W)*
R/(W)*
Description
Erroneous stop-condition detected
The ESTP flag indicates that the stop condition has been
detected during the transfer of a frame, in the I²C bus format
in the slave mode.
0: Erroneous-stop condition is not present
[Clearing condition]
(1) Writing of 0 to this bit after reading ESTP = 1
(2) Clearing of the IRIC flag to 0
1: An erroneous-stop condition has been detected in the I²C
bus format in the slave mode (this value has no meaning
when the interface is not in the I²C bus format in the slave
mode).
[Setting condition]
Detection of the stop condition during the transfer of a frame
Normal stop-condition detection flag
The STOP flag indicates that the stop condition has been
detected after the transfer of a frame in the I²C bus format in
the slave mode.
0: Normal stop-condition is not present.
[Clearing conditions]
(1) Writing of 0 to this bit after reading STOP = 1
(2) Clearing of the IRIC flag to 0
1: The normal stop condition has been detected in the I²C
bus format in the slave mode (this value has no meaning
when the interface is not in the I²C bus format in the slave
mode).
[Setting condition]
Detection of the stop condition after the transfer of a frame
Rev. 2.0, 09/02, page 429 of 732