SH7144 Datasheet, PDF (104/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

5.6.1 Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction placed immediately after it (delay slot) are always executed consecutively, so no
exception processing occurs during this period.
5.6.2 Immediately after an Interrupt-Disabled Instruction
When an instruction placed immediately after an interrupt-disabled instruction is decoded,
interrupts are not accepted. Address errors can be accepted.
Rev. 2.0, 09/02, page 64 of 732