SH7144 Datasheet, PDF (710/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

26.3.2 Clock timing
Table 26.4 shows the clock timing.
Table 26.4 Clock Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Operating frequency
Clock cycle time
Clock low-level pulse width
Clock high-level pulse width
Clock rise time
Clock fall time
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
Reset oscillation settling time
Standby return oscillation settling time
Clock cycle time for peripheral modules
Symbol
f_op
t_cyc
t_CL
t_CH
t_CR
t_CF
f_EX
t_EXcyc
t_EXL
t_EXH
t
EXR
t_EXF
t_OSC1
t_OSC2
t_pcyc
Min
Max
4
50
20
250
1/2 t_cyc−5 
1/2 t_cyc−5 

5

5
4
12.5
80
250
35

35


5

5
10

10

25
500
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ms
ms
ns
Figure
Figure 26.2
Figure 26.3
Figure 26.4
t_cyc
t_CH
t_CL
V_OH
CK
1/2V_CC
V_OH
V_OL
t_CF
V_OH
1/2V_CC
V_OL
t_CR
Figure 26.2 System Clock Timing
Rev. 2.0, 09/02, page 670 of 732