SH7144 Datasheet, PDF (427/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
All data transmitted?
Yes
Read TEND flag in SSR
No
[3]
TEND = 1
Yes
Break output?
Yes
Clear DR to 0
No
No
[4]
[1] SCI initialization:
Set the TxD pin using the PFC.
After the TE bit is set to 1, a frame
period of 1s is output, and
transmission is enabled. This action
doesn't initiate immediate data
transmission.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear
the TDRE flag to 0. Checking and
clearing of the TDRE flag is
automatic when the DMAC or DTC
is activated by a transmit data
empty interrupt (TXI) request, and
data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then clear
the TE bit to 0 in SCR and use the
PFC to select the TxD pin as an
Clear TE bit in SCR to 0;
select the TxD pin
as an output port with the PFC
<End>
Figure 13.7 Sample Serial Transmission Flowchart
Rev. 2.0, 09/02, page 387 of 732