SH7144 Datasheet, PDF (399/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

12.6.2 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation.
TCNT write cycle
T1
T2
T3
φ
Address
TCNT address
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
12.6.3 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while
the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by
clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0.
12.6.4 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
Rev. 2.0, 09/02, page 359 of 732