SH7144 Datasheet, PDF(38/773 Page) Renesas Technology Corp – Hitachi SuperH RISC engine

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SH7144 Datasheet, PDF (38/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

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Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ................... 378

Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ................... 378

Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3) ................... 379

Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4) ................... 379

Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ........ 380

Table 13.8 Serial Transfer Formats (Asynchronous Mode)........................................................ 382

Table 13.9 SSR Status Flags and Receive Data Handling .......................................................... 389

Table 13.10 SCI Interrupt Sources.............................................................................................. 407

Section 14 I2C Bus Interface (IIC) Option

Table 14.1 Pin Configuration...................................................................................................... 413

Table 14.2 Transfer Format ........................................................................................................ 417

Table 14.3 Setting of the Transfer Clock.................................................................................... 420

Table 14.4 Setting of the Bit Counter ......................................................................................... 420

Table 14.5 Description of IRIC .................................................................................................. 426

Table 14.6 The Relationship between Flags and Transfer States ............................................... 428

Table 14.7 I2C Bus Data Format: Description of Symbols ......................................................... 437

Table 14.8 Examples of Operations in which the DTC is Used ................................................. 449

Table 14.9 I2C Bus Timing (output of SCL and SDA) ............................................................... 454

Table 14.10 Tolerance of the SCL Rise Time (tSr) ..................................................................... 455

Table 14.11 I2C Bus Timing (when the effect of tSr/tSf is at its maximum) ................................ 456

Section 15 A/D Converter

Table 15.1 Pin Configuration...................................................................................................... 465

Table 15.2 Channel Select List ................................................................................................... 468

Table 15.3 A/D Conversion Time (Single Mode)....................................................................... 473

Table 15.4 A/D Conversion Time (Scan Mode) ......................................................................... 474

Table 15.5 A/D Converter Interrupt Source................................................................................ 475

Table 15.6 Analog Pin Specifications......................................................................................... 479

Section 17 Pin Function Controller (PFC)

Table 17.1 SH7144 Multiplexed Pins (Port A)........................................................................... 489

Table 17.2 SH7144 Multiplexed Pins (Port B) ........................................................................... 490

Table 17.3 SH7144 Multiplexed Pins (Port C) ........................................................................... 490

Table 17.4 SH7144 Multiplexed Pins (Port D)........................................................................... 491

Table 17.5 SH7144 Multiplexed Pins (Port E) ........................................................................... 492

Table 17.6 SH7144 Multiplexed Pins (Port F) ........................................................................... 492

Table 17.7 SH7145 Multiplexed Pins (Port A)........................................................................... 493

Table 17.8 SH7145 Multiplexed Pins (Port B) ........................................................................... 494

Table 17.9 SH7145 Multiplexed Pins (Port C) ........................................................................... 494

Table 17.10 SH7145 Multiplexed Pins (Port D)......................................................................... 495

Table 17.11 SH7145 Multiplexed Pins (Port E) ......................................................................... 496

Table 17.12 SH7145 Multiplexed Pins (Port F) ......................................................................... 496

Table 17.13 SH7144 Pin Functions in Each Mode (1) ............................................................... 497

Rev. 2.0, 09/02, page xxxvi of xxxviii

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