SH7144 Datasheet, PDF (142/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

7.5.3 Contention between User Break and Exception Processing
If a user break is set for the fetch of a particular instruction, and exception processing with higher
priority than a user break is in contention and is accepted in the decode stage for that instruction
(or the next instruction), user break exception processing may not be performed after completion
of the higher-priority exception service routine (on return by RTE).
Thus, if a user break condition is specified to the branch destination instruction fetch after a
branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception
processing), and that branch instruction accepts an exception processing with higher priority than
a user break interrupt, user break exception processing is not performed after completion of the
exception service routine.
Therefore, a user break condition should not be set for the fetch of the branch destination
instruction after a branch.
7.5.4 Break at Non-Delay Branch Instruction Jump Destination
When a branch instruction without delay slot (including exception processing) jumps to the
destination instruction by executing the branch, a user break will not be generated even if a user
break condition has been set for the first jump destination instruction fetch.
7.5.5 Module Standby Mode Setting
The UBC can set the module disable/enable by using the module standby control register 2
(MSTCR2). By releasing the module standby mode, register access becomes to be enabled.
By setting the MSTP0 bit of MSTCR2 to 1, the UBC is in the module standby mode in which the
clock supply is halted. See section 24, Power-Down State, for further details.
Rev. 2.0, 09/02, page 102 of 732