SH7144 Datasheet, PDF (646/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Serial data
Instruc-
Input/
tion SDTRF Input
output
1
0
1
H-UDI interrupt
request
SDTRF
(in SDSR)^*1
Shift
enabled
SDSR and SDDR
MUX^*2
SDDR access
state
SDSR
Shift
disabled _Shift
enabled
SDDR
SDSR
SDDR
Shift
CPU
Shift
CPU
SDSR serial transfer
(monitoring)
Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer
data input/output to SDDR is possible.
1 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0.
0 SDDR is shift-disabled. SDDR access by the CPU is enabled.
Conditions: • SDTRF = 1
— When
=0
— When the CPU writes 1
— In bypass mode
• SDTRF = 0
— End of SDDR shift access in serial transfer
2. SDSR/SDDR (Update-DR state) internal MUX switchover timing
• Switchover from SDSR to SDDR: On completion of serial transfer in which
SDTRF = 1 is output from TDO
• Switchover from SDDR to SDSR: On completion of serial transfer to SDDR
Figure 22.2 Data Input/Output Timing Chart (1)
Rev. 2.0, 09/02, page 606 of 732