SH7144 Datasheet, PDF (392/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
5
TME
0
R/W Timer Enable
Enables or disables the timer.
0: Timer disabled
TCNT is initialized to H'00 and count-up stops
1: Timer enabled
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
4
—
1
R
Reserved
3
—
1
R
This bit is always read as 1 and cannot be modified.
2
CKS2
0
R/W Clock Select 2 to 0
1
CKS1
0
0
CKS0
0
R/W Select one of eight internal clock sources for input to
R/W
TCNT. The clock signals are obtained by dividing the
frequency of the system clock (φ). The overflow
frequency for φ = 40 MHz is enclosed in
parentheses*².
000: Clock φ/2 (overflow interval: 12.8 µs)
001: Clock φ/64 (overflow interval: 409.6 µs)
010: Clock φ/128 (overflow interval: 0.8 ms)
011: Clock φ/256 (overflow interval: 1.6 ms)
100: Clock φ/512 (overflow interval: 3.3 ms)
101: Clock φ/1024 (overflow interval: 6.6 ms)
110: Clock φ/4096 (overflow interval: 26.2 ms)
111: Clock φ/8192 (overflow interval: 52.4 ms)
Notes: 1. Only a 0 can be written after reading 1.
2. The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev. 2.0, 09/02, page 352 of 732