SH7144 Datasheet, PDF (421/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

13.4 Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the communication line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver
are independent units, enabling full-duplex communication. Both the transmitter and the receiver
also have a double-buffered structure, so that data can be read or written during transmission or
reception, enabling continuous data transfer.
Idle state
(mark state)
1
LSB
MSB
1
Serial
data
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Start
bit
Transmit/receive data
Parity
bit Stop bit
1 bit
7 or 8 bits
1 bit 1 or 2 bits
or
none
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
Rev. 2.0, 09/02, page 381 of 732