SH7144 Datasheet, PDF (712/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

26.3.3 Control Signal Timing
Table 26.5 shows control signal timing.
Table 26.5 Control Signal Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min
RES rise time, fall time
t , t _{RESr RESf}

RES pulse width
t_RESW
25
RES setup time
t_RESS
35
MRES pulse width
t_MRESW
20
MRES setup time
t_MRESS
35
MD3 to MD0 setup time
t_MDS
20
NMI rise time, fall time
t , t _{NMIr NMIIf}

NMI setup time
t_NMIS
35
NMI hold time
t_NMIH
35
IRQ7 to IRQ0 setup time* (edge detection) t_IRQES
19
IRQ7 to IRQ0 setup time* (level detection)
t
IRQLS
19
IRQ7 to IRQ0 hold time
t_IRQEH
19
IRQOUT output delay time
t_IRQOD

Bus request setup time
t_BRQS
19
Bus acknowledge delay time 1
t_BACKD1

Bus acknowledge delay time 2
t
BACKD2

Bus three-state delay time
t
BZD

Max
200





200





100

35
35
35
Unit
ns
t_cyc
ns
t_cyc
ns
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Figure 26.5
Figure 26.6
Figure 26.7
Figure 26.8
[Operating Precautions]
Note: * The RES, MRES, NMI and IRQ7 to IRQ0 signals are asynchronous inputs, but when the
setup times shown here are observed, the signals are considered to have been changed at
clock rise (RES, MRES) or fall (NMI and IRQ7 to IRQ0). If the setup times are not
observed, the recognition of these signals may be delayed until the next clock rise or fall.
Rev. 2.0, 09/02, page 672 of 732