SH7144 Datasheet, PDF (153/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Through DTC activation, a register information start address is read from the vector table, then
register information placed in memory space is read from that register information start address.
Always designate register information start addresses in multiples of four.
DTBR
Transfer information
start address
(upper 16 bits)
DTC vector table
DTC vector address
Register information
start address
(lower 16 bits)
Memory space
Register
information
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs
Activating
Source
Generator
MTU (CH4)
MTU (CH3)
MTU (CH2)
MTU (CH1)
Activating
Source
TGIA_4
TGIB_4
TGIC_4
TGID_4
TCIV_4
TGIA_3
TGIB_3
TGIC_3
TGID_3
TGIA_2
TGIB_2
TGIA_1
TGIB_1
DTC Vector
Address
H'00000400
H'00000402
H'00000404
H'00000406
H'00000408
H'0000040A
H'0000040C
H'0000040E
H'00000410
H'00000412
H'00000414
H'00000416
H'00000418
DTE Bit
DTEA7
DTEA6
DTEA5
DTEA4
DTEA3
DTEA2
DTEA1
DTEA0
DTEB7
DTEB6
DTEB5
DTEB4
DTEB3
Transfer
Source
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Transfer
Destination Priority
Arbitrary* High
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary*
Arbitrary* Low
Rev. 2.0, 09/02, page 113 of 732