SH7144 Datasheet, PDF (479/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

When continuously transmitting data,
6. Clear the IRIC flag to 0 before the rising edge of the 9th cycle of the transmission clock for the
data being transmitted, and write the next datum for transmission to ICDR.
7. When the transmission of one frame of data has been completed, the IRIC flag in ICCR is set
to 1 on the rising edge of the 9th cycle of the transmission clock. Concurrently, the next datum
for transmission is transferred from ICDR (ICDRT) to ICDRS, the internal TDRE flag is set to
1, and the next frame is transmitted in synchronization with the internal clock.
Steps 6 and 7 are repeated for the continuous transmission of data.
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
1
2
3
4
5
6
7
8
9
1
2
3
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data1
Bit7 Bit6 Bit5
[7]
Data2
A
IRIC
Interrupt-request
generation
ICDRT
ICDRS
Data1
Data1
Data2
[7]
Data2
Data3
User processing
ICDR write
[6] IRIC clear [6] ICDR write
[6] IRIC clear [6] ICDR write
Note: The numbers in brackets [ ] represent step numbers in the above procedural description.
Figure 14.7 An Example of the Continuous Transmission Timing in
Master-Transmission Mode (MLS = WAIT = 0)
Rev. 2.0, 09/02, page 439 of 732