SH7144 Datasheet, PDF (465/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name
Initial
Value R/W
Description
1 IRIC
0
R/(W)*
I²C-bus-interface interrupt-request flag
The IRIC flag indicates that the I²C bus interface has
generated an interrupt request for the CPU. When the slave
address or the general call address is detected in slave-
reception mode after the transfer of data has been
completed, when there is a failure because of bus conflict in
the master-transmission mode, and when the stop condition
is detected, the IRIC flag is set to 1. The timing with which
the IRIC flag is set changes according to the combination of
the values of the FS bit in SAR and the WAIT bit in ICMR.
Refer to section 14.4.6, Timing for Setting IRIC and the
Control of SCL. In addition, the condition on which the IRIC
flag is set changes according to the setting of the ACKE bit in
ICCR.
The IRIC flag is cleared by reading 1 from IRIC and then
writing 0.
When the DTC is used, the IRIC flag is automatically cleared;
this allows transfer to be continuous and without the
intervention of the CPU.
0: Transfer-wait state or during a transfer
1: An interrupt is generated.
For details, refer to table 14.5, Description of IRIC.
0 SCP
1
W
Start/stop condition issuance disabling bit
This bit controls issuing of the start/stop-condition signals in
master mode. When setting the start condition, write 1 to
BBSY and 0 to SCP. When re-transmitting the start condition,
follow the same procedure. The stop condition is set by
writing 0 to BBSY and SCP. When this bit is read, it always
returns 1. 1 written to this bit will not be stored.
0: In combination with the BBSY flag, issues the start/stop-
condition signals during writing.
1: When read, 1 is always returned. Writing to this bit is not a
valid operation.
Note: * It is only possible to write a 0 to this bit, to clear the flag.
Rev. 2.0, 09/02, page 425 of 732