SH7144 Datasheet, PDF (410/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
5
ORER
0
R/(W)* Overrun Error
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
4
FER
0
R/(W)* Framing Error
[Setting condition]
• When the stop bit is 0
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
The FER flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
3
PER
0
R/(W)* Parity Error
[Setting condition]
• When a parity error is detected during reception
[Clearing condition]
• Power-on reset or software standby mode
• When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains their
previous values when the RE bit in SCR is cleared to
0.
Rev. 2.0, 09/02, page 370 of 732