SH7144 Datasheet, PDF (168/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

9.4 Address Map
Figure 9.2 shows the address format used by this LSI.
A31 to A24
A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs to
when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS space when 00000000 (H'00)
Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 9.2 Address Format
This chip uses 32-bit addresses:
• Bits A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS3 to CS0) for the
corresponding areas when bits A31 to A24 are 00000000.
• A21 to A0 are output externally.
Table 9.2 shows the address map.
Table 9.2 Address Map
On-chip ROM enabled mode
Address
H'00000000 to H'0003FFFF
H'00040000 to H'001FFFFF
H'00200000 to H'003FFFFF
H'00400000 to H'007FFFFF
H'00800000 to H'00BFFFFF
H'00C00000 to H'00FFFFFF
H'01000000 to H'FFFF7FFF
H'FFFF8000 to H'FFFFBFFF
H'FFFFC000 to H'FFFFDFFF
H'FFFFE000 to H'FFFFFFFF
Space
Memory
Size
On-chip ROM
On-chip ROM
256 kbytes
Reserved
Reserved
CS0 space
External space
2 Mbytes
CS1 space
External space
4 Mbytes
CS2 space
External space
4 Mbytes
CS3 space
External space
4 Mbytes
Reserved
Reserved
On-chip peripheral On-chip peripheral 16 kbytes
module
module
Reserved
Reserved
On-chip RAM
On-chip RAM
8 kbytes
Bus Width
32 bits
8/16/32 bits*¹
8/16/32 bits*¹
8/16/32 bits*¹
8/16/32 bits*¹
8/16 bits
32 bits
Rev. 2.0, 09/02, page 128 of 732