SH7144 Datasheet, PDF (662/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 24.1 Internal Operation States in Each Mode
Function
Normal Operation Sleep
Module Standby Software Standby
System clock pulse generator Functioning
Functioning

Halted
CPU
Functioning
Halted (retained) 
Halted (retained)
External
interrupts
NMI
Functioning
IRQ7 to IRQ0
Functioning

Functioning
Peripheral
functions
UBC
DMAC
Functioning
Functioning
Functioning
Functioning
Halted (reset)
Halted (reset)
Halted (retained)
Halted (reset)
DTC
IIC
I/O port
Functioning
Functioning

Halted (retained)
WDT
Functioning
Functioning

Halted (retained)
SCI
Functioning
Functioning
Halted (reset)
Halted (reset)
A/D
MTU
CMT
H-UDI
Functioning
Functioning
Halted (retained) Halted (retained)
AUD
Functioning
Functioning
Halted (reset)
Halted (reset)
ROM
RAM
Functioning
Functioning
Halted (retained) Halted (retained)
Notes: 1. "Halted (retained)" means that the operation of the internal state is suspended, although
internal register values are retained.
2. "Halted (reset)" means that internal register values and internal state are initialized.
3. In module standby mode, only modules for which a stop setting has been made are
halted (reset or retained).
4. There are two types of on-chip peripheral module registers; ones which are initialized
by module standby mode or software standby mode, and those not initialized by that
mode. For details, refer to section 25.3, Register States in Each Operating Mode.
5. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port in software
standby mode. For details on the setting, refer to section 24.2.1, Standby Control
Register (SBYCR). For the state of pins, refer to Appendix A, Pin States.
Rev. 2.0, 09/02, page 622 of 732