SH7144 Datasheet, PDF (724/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

26.3.9 Serial Communication Interface (SCI)Timing
Table 26.11 shows serial communication interface timing.
Table 26.11 Serial Communication Interface Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min
Input clock cycle
t_scyc
4
Input clock cycle (clock sync) t_scyc
6
Input clock pulse width
t_sckw
0.4
Input clock rise time
t_sckr

Input clock fall time
t_sckf

Transmit data delay time
t_TxD

Received data setup time
t_RxS
100
Received data hold time
t_RxH
100
Max


0.6
1.5
1.5
100


Unit
t_pcyc
t_pcyc
t_scyc
t_pcyc
t_pcyc
ns
ns
ns
Figure
Figure 26.19
Figure 26.20
[Operating Precautions]
The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 26.19, the
received data is considered to have been changed at CK clock rise (two-clock intervals). The
transmit signals change with a reference of CK clock rise (two-clock intervals).
SCK0 to SCK3
t_sckw
V_IH
V_IH
V_IL
t_sckr
V_IH
V_IL
t_scyc
t_sckf
V_IH
V_IL
Figure 26.19 SCI Input Timing
Rev. 2.0, 09/02, page 684 of 732