SH7144 Datasheet, PDF (657/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

23.4.2 Communication Protocol
The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
Input format
0000
DIR A3 to A0 ^{. . . . . .} A31 to A28 D3 to D0 ^{. . . . . .} Dn to Dn-3
Command
Address
Data (in case of write only)
B write: n = 7
W write: n = 15
L write: n = 31
Bit 3
Bit 2
Fixed at 1 0: Read
1: Write
Bit 1 Bit 0
00: Byte
01: Word
10: Longword
Spare bits (4 bits): b'0000
Figure 23.4 AUDATA Input Format
23.4.3 Operation
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, then
AUDRST is negated.
Figure 23.5 shows an example of a read operation, and figure 23.6 an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 23.4, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (0000).
When execution is completed, the Ready flag (0001) is returned (figures 23.5 and 23.6). Table
23.2 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 23.5).
If a command other than the above is input in DIR, the AUD treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the
Ready flag to 1 (figure 23.7).
Bus error conditions are shown below.
Rev. 2.0, 09/02, page 617 of 732