SH7144 Datasheet, PDF (463/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name
4 TRS
Initial
Value R/W
0
R/W
Description
Selects transmission/reception
This bit determines whether the I²C bus interface is used in
receive mode or in transmit mode.
0: Receive mode
[Clearing conditions]
(1) Writing of 0 to this bit by software (except when the 1 was
set by setting condition (3))
(2) 0 is written after TRS = 1 is read (when the 1 was set by
setting condition (3))
(3) When the master device in the I²C bus format starts
transmission and then fails because of a bus conflict.
1: Transmit mode
[Setting conditions]
(1) Writing of 1 to this bit by software (except when the 1 was
set by clearing condition (3))
(2) Writing of 1 to this bit after reading TRS = 0 (when the 0
was set by clearing condition (3))
(3) When 1 is received as the R/W bit of the first frame in the
I²C bus format in slave mode.
When the addressing format (FS = 0 or FSX = 0) is used in the
slave-receive mode, transmission or reception is automatically
selected by the hardware, according to the setting of the R/W
bit of the first frame after the start condition has been satisfied.
Even if an attempt is made to change the TRS bit during the
transfer of data, the change is suspended until transmission of
the frame, including the acknowledge bit, has been completed;
the bit is then changed.
Rev. 2.0, 09/02, page 423 of 732