SH7144 Datasheet, PDF (180/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the Tw state shifts to the T2 state.
CK
Address
T1
Tw
Tw
Two
T2
Read
Data
Write
Data
DACK
Figure 9.5 Wait State Timing of External Space Access
(Two Software Wait States + WAIT Signal Wait State)
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