SH7144 Datasheet, PDF (211/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

CK
A21–A0
D15–D0
Transfer source
address
Transfer destination
address
,
DACK
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: Transfer between external memories with DACK are output during read cycle.
Figure 10.7 Example of Direct Address Transfer Timing in Dual Address Mode
Indirect Address Transfer Mode: In this mode the memory address storing the data you actually
want to transfer is specified in DMAC internal transfer source address register (SAR3). Therefore,
in indirect address transfer mode, the DMAC internal transfer source address register value is read
first. This value is stored once in the DMAC. Next, the read value is output as the address, and the
value stored at that address is again stored in the DMAC. Finally, the subsequent read value is
written to the address specified by the transfer destination address register, ending one cycle of
DMA transfer.
In indirect address mode (figure 10.8), transfer destination, transfer source, and indirect address
storage destination are all 16-bit external memory locations, and transfer in this example is
conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 10.9.
In indirect address mode, one NOP cycle (figure 10.9) is required until the data read as the indirect
address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles
each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole
operation.
Rev. 2.0, 09/02, page 171 of 732