SH7144 Datasheet, PDF (215/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bus Modes
Select the appropriate bus mode in the TM bits of CHCR0 to CHCR3. There are two bus modes:
cycle steal and burst.
Cycle-Steal Mode: In the cycle steal mode, the bus mastership is given to another bus master after
each one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request
occurs, the bus mastership are obtained from the other bus master and a transfer is performed for
one transfer unit. When that transfer ends, the bus mastership is passed to the other bus master.
This is repeated until the transfer end conditions are satisfied.
The cycle steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 10.11 shows an example of DMA transfer timing in the cycle steal mode.
Transfer conditions are dual address mode and DREQ level detection.
Bus control returned to CPU
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read Write
CPU DMAC DMAC CPU
Read Write
CPU
Figure 10.11 DMA Transfer Example in the Cycle-Steal Mode
Burst Mode: Once the bus mastership is obtained, the transfer is performed continuously until the
transfer end condition is satisfied. In the external request mode with low level detection of the
DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master
after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the
transfer end conditions have not been satisfied.
Figure 10.12 shows an example of DMA transfer timing in the burst mode. Transfer conditions are
single address mode and DREQ level detection.
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 10.12 DMA Transfer Example in the Burst Mode
Rev. 2.0, 09/02, page 175 of 732