SH7144 Datasheet, PDF (386/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

8/16/128 clock
cycles
P
Sampling
clock
input
PE9/
TIOC3B
High-impedance
state*
When low level is
Flag set
sampled at all points ¹
2
3
16 _{( received)}
When high level is
1
2
sampled at least once
13 Flag not set
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/
, PE14/TIOC4C,
PE15/TIOC4D/
) also go to the high-impedance state at the same timing.
Figure 11.115 Low-Level Detection Operation
Output-Level Compare Operation
Figure 11.116 shows an example of the output-level compare operation for the combination of
PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations.
P
PE9/
TIOC3B
PE11/
TIOC3D
Low level overlapping detected
High impedance state
Figure 11.116 Output-Level Detection Operation
Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become high-
impedance due to output-level detection can be released either by returning them to their initial
state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level
compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance
state by clearing the OSF flag, always do so only after outputting a high level from the high-
current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs
can be achieved by setting the MTU internal registers.
Rev. 2.0, 09/02, page 346 of 732