SH7144 Datasheet, PDF (478/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

4. When the transmission of one frame has been completed, the IRIC flag is set to 1 on the rising
edge of the 9th cycle of the transmission clock. When the internal TDRE flag is set to 1 after
one frame has been transmitted, the level on SCL is automatically fixed low in synchronization
with the internal clock until the next datum for transmission has been written to ICDR.
5. When transmission is to be continued, the next datum for transmission is written to ICDR.
After that datum has been transferred to ICDRS and the internal TDRE flag has been set to 1,
clear the IRIC flag to 0. The next frame will be transmitted in synchronization with the internal
clock.
Data can be sequentially transmitted by repeatedly performing steps 4 and 5 above. When
terminating the transmission, clear the IRIC flag, write the H’FF to ICDR as a dummy after the
transmission of the final frame of data has been completed (when there is no further data for
transmission in ICDRT), then write 0 to the BBSY and SCP bits of ICCR to 0 at the point after the
IRIC flag has been set. When SCL is high, the level on SDA is changed from low to high to create
the stop condition.
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TDRE
Start condition in place
1
2
3
4
5
6
7
8
9
Slave address
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
[4]
Slave address
R/W
A
1
2
Bit7 Bit6
Data1
IRIC
Interrupt-request
generation
Interrupt-request
generation
ICDRT
Address+R/W
Data1
ICDRS
Address+R/W
Data1
User processing [2] Write 1 to BBSY and [3] ICDR write
0 to SCP (put the
start condition in place)
[3] IRIC clear
[5] ICDR write
Note: The numbers in brackets [ ] represent step numbers in the above procedural description.
[5] IRIC clear
Figure 14.6 An Example of the Timing of Operations in Master-Transmission Mode
(MLS = WAIT = 0)
Rev. 2.0, 09/02, page 438 of 732