SH7144 Datasheet, PDF (125/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

6.7 Interrupt Response Time
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3 Interrupt Response Time
Item
DMAC/DTC active
judgment
Number of States
NMI, Peripheral
Module
IRQ
0 or 1
1
Interrupt priority judgment 2
and comparison with SR
mask bits
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
3
X (≥ 0)
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
5 + m1 + m2 + m3
Remarks
1 state required for interrupt
signals for which
DMAC/DTC activation is
possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the saving PC and
SR, and vector address
fetch.
Interrupt
response
time
Total: (7 or 8) + m1 +
m2 + m3+X
Minimum: 10
9 + m1 + m2 +
m3 + X
12
0.20 to 0.24 µs at 50 MHz
Maximum: 12 + 2 (m1 + m2
+ m3) + m4
13 + 2 (m1 + m2
+ m3) + m4
0.38 to 0.40 µs at 50 MHz*
Note:
m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* 0.38 to 0.40 µs at 50 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
Rev. 2.0, 09/02, page 85 of 732