SH7144 Datasheet, PDF (481/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Master-transmission mode Master-reception mode
SCL
(Master output) 9
SDA
(Slave output)
A
SDA
(Master output)
1
2
3
4
5
6
7
8
9
1
2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data1
Bit7 Bit6
[3]
Data2
A
RDRF
IRIC
ICDRS
Interrupt-request
generation
Interrupt-request
generation
Data1
ICDRR
Data1
User processing
[1] TRS is cleared to 0
[2] ICDR read [2] IRIC clear
(dummy read)
[4] ICDR read [4] IRIC clear
Note: The numbers in brackets [ ] represent step numbers in the above procedural description.
Figure 14.8 An Example of the Timing of Operations in Master-Reception Mode
(MLS = WAIT = ACKB = 0)
Rev. 2.0, 09/02, page 441 of 732