SH7144 Datasheet, PDF (719/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

26.3.5 Direct Memory Access Controller (DMAC) Timing
Table 26.7 shows direct memory access controller timing.
Table 26.7 Direct Memory Access Controller Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
DREQ0, DREQ1 setup time
DREQ0, DREQ1 hold time
DREQ0, DREQ1 pulse width
DRAK0, DRAK1 output delay time
Symbol
t
DRQS
t
DRQH
t_DRQW
t_DRAKD
Min
10
1.5 t_cyc−10
1.5

Max



30
Unit
ns
ns
t_cyc
ns
Figure
Figure 26.12
Figure 26.13
Figure 26.14
CK
level input
edge input
t_DRQS
t_DRQS
t_DRQH
t_DRQS
level cancel
Figure 26.12 DREQ0, DREQ1 Input Timing (1)
Rev. 2.0, 09/02, page 679 of 732