SH7144 Datasheet, PDF (175/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
4
CW0
1
R/W Idle cycles at continuous access to CS0 space
This bit inserts an idle cycle and negates the CS0 signal to
make the bus cycle end obvious when accessing the CS0
space continuously.
0: No idle cycle inserted at continuous access to the CS0
space.
1: One idle cycle inserted at continuous access to the CS0
space.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
3
SW3
1
R/W CS assert period extension for CS3 space
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS3.
0: No cycle inserted for CS assert period.
1: CS assert extension (each one cycle inserted before and
after the bus cycle).
2
SW2
1
R/W CS assert period extension for CS2 space
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS2.
0: No cycle inserted for CS assert period.
1: CS assert extension (each one cycle inserted before and
after the bus cycle).
1
SW1
1
R/W CS assert period extension for CS1 space
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS1.
0: No cycle inserted for CS assert period.
1: CS assert extension (each one cycle inserted before and
after the bus cycle).
0
SW0
1
R/W CS assert period extension for CS0 space
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS0.
0: No cycle inserted for CS assert period.
1: CS assert extension (each one cycle inserted before and
after the bus cycle).
Rev. 2.0, 09/02, page 135 of 732