SH7144 Datasheet, PDF (243/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 11.9 MD0 to MD3
Bit 3
MD3
Bit 2
MD2
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Setting prohibited
1
0
PWM mode 1
1
PWM mode 2*¹
1
0
0
Phase counting mode 1*²
1
Phase counting mode 2*²
1
0
Phase counting mode 3*²
1
Phase counting mode 4*²
1
0
0
0
Reset synchronous PWM mode*³
1
Setting prohibited
1
X
Setting prohibited
1
0
0
Setting prohibited
1
Complementary PWM mode 1 (transmit at peak)*³
1
0
Complementary PWM mode 2 (transmit at valley)*³
1
Complementary PWM mode 2 (transmit at peak and valley)*³
Legend:
X: Don’t care
Notes: 1. PWM mode 2 can not be set for channels 3, 4.
2. Phase counting mode can not be set for channels 0, 3, 4.
3. Reset synchronous PWM mode, complementary PWM mode can only be set for
channel 3. When channel 3 is set to reset synchronous PWM mode or complementary
PWM mode, the channel 4 settings become ineffective and automatically conform to the
channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or
complementary PWM mode. Reset synchronous PWM mode and complementary PWM
mode can not be set for channels 0, 1, 2.
11.3.3 Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev. 2.0, 09/02, page 203 of 732