SH7144 Datasheet, PDF (619/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

19.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing.
Bit Bit Name Initial Value R/W
7
FLER
0
R
6 to 0 —
All 0
R
Description
Indicates that an error has occurred during an
operation on flash memory (programming or erasing).
When FLER is set to 1, flash memory goes to the
error-protection state.
See section 19.9.3, Error Protection, for details.
Reserved
These bits are always read as 0.
19.5.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase block. EBR1 is initialized to H’00 when a high level is
input to the FWP pin. It is also initialized to H’00, when the SWE bit in FLMCR1 is 0 regardless
of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will
cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Bit Bit Name Initial Value R/W Description
7
EB7
0
R/W When this bit is set to 1, 4 kbytes of EB7 (H’007000
to H’007FFF) are to be erased.
6
EB6
0
R/W When this bit is set to 1, 4 kbytes of EB6 (H’006000
to H’006FFF) are to be erased.
5
EB5
0
R/W When this bit is set to 1, 4 kbytes of EB5 (H’005000
to H’005FFF) are to be erased.
4
EB4
0
R/W When this bit is set to 1, 4 kbytes of EB4 (H’004000
to H’004FFF) are to be erased.
3
EB3
0
R/W When this bit is set to 1, 4 kbytes of EB3 (H’003000
to H’003FFF) are to be erased.
2
EB2
0
R/W When this bit is set to 1, 4 kbytes of EB2 (H’002000
to H’002FFF) are to be erased.
1
EB1
0
R/W When this bit is set to 1, 4 kbytes of EB1 (H’001000
to H’001FFF) are to be erased.
0
EB0
0
R/W When this bit is set to 1, 4 kbytes of EB0 (H’000000
to H’000FFF) are to be erased.
Rev. 2.0, 09/02, page 579 of 732