SH7144 Datasheet, PDF (476/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

(a) FS=0 or FSX=0
S
SLA
1
7
R/
A
1
1
1
DATA
n
A
1
m
A/
P
1
1
Number of bits
being transferred
(n=1 to 8)
Number of frames
being transferred
(m=1 or above)
(b) When the start condition is re-transmitted, FS=0 or FSX=0
S
SLA
R/
A
DATA
1
7
11
n1
A/ S
11
1
m1
SLA
R/
A
DATA
7
11
n2
A/ P
11
1
m2
Upper: Number of bits being transferred (n=1, n2=1 to 8)
Lower: Number of frames being transferred (m=1, m2=1 or above)
Figure 14.3 I²C Bus Data Format 1 (I²C Bus Format)
FS=1 and FSX=1
S
DATA
1
8
1
DATA
n
m
P
1
Number of bits
being transferred
(n=1 to 8)
Number of frames
being transferred
(m=1 or above)
Figure 14.4 I²C Bus Data Format 2 (Serial Format)
SDA
SCL
S
1-7
8
9
1-7
8
9
1-7
8
9
SLA
R/W A
DATA
A
Figure 14.5 I²C Bus Timing
DATA
A/A
P
Rev. 2.0, 09/02, page 436 of 732