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SH7144 Datasheet, PDF (620/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine | |||
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19.5.4 Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase block. EBR2 is initialized to Hâ00 when a high level is
input to the FWP pin. It is also initialized to Hâ00, when the SWE bit in FLMCR1 is 0 regardless
of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will
cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Bit
Bit Name Initial Value R/W
7 to 4 â
All 0
R
3
EB11
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
0
EB8
0
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0
When this bit is set to 1, 64 kbytes of EB11
(Hâ030000 to Hâ03FFFF) are to be erased.
When this bit is set to 1, 64 kbytes of EB10
(Hâ020000 to Hâ02FFFF) are to be erased.
When this bit is set to 1, 64 kbytes of EB9 (Hâ010000
to Hâ01FFFF) will be erased.
When this bit is set to 1, 32 kbytes of EB8 (Hâ008000
to Hâ00FFFF) will be erased.
19.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Bit
Bit Name Initial Value R/W
15 to 4 â
All 0
R
3
RAMS 0
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0
RAM Select
Specifies selection or non-selection of flash memory
emulation in RAM. When RAMS = 1, the flash
memory is overlapped with part of RAM, and all flash
memory blocks are program/erase-protected. When
RAMS = 0, the RAM emulation function is disabled.
Rev. 2.0, 09/02, page 580 of 732
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