SH7144 Datasheet, PDF (149/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

8.2.6 DTC Transfer Count Register B (DTCRB)
The DTCRB is a 16-bit register that designates the block length in block transfer mode. The block
length is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000.
The initial value of DTCRB is undefined.
8.2.7 DTC Enable Registers (DTER)
DTER which is comprised of six registers, DTEA to DTEE, DTEG, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTE bits is
shown in table 8.1.
Bit Bit Name Initial Value R/W Description
7
DTE*7
0
R/W DTC Activation Enable
6
DTE*6
0
5
DTE*5
0
4
DTE*4
0
3
DTE*3
0
2
DTE*2
0
1
DTE*1
0
0
DTE*0
0
R/W Setting this bit to 1 specifies the corresponding
R/W ^{interrupt source to a DTC activation source.}
R/W ^{[Clearing conditions]}
R/W ^{• When the DISEL bit is 1 and the data transfer has}
R/W
ended
R/W ^{• When the specified number of transfers have}
ended
R/W
• 0 is written to the bit to be cleared after 1 has been
read from the bit
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended.
[Setting condition]
1 is written to the bit to be set after a 0 has been read
from the bit
Note: * The last character of the DTC enable register’s name comes here.
Example: DTEB3 in DTEB, etc.
Rev. 2.0, 09/02, page 109 of 732