SH7144 Datasheet, PDF (381/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit
Bit Name Initial value R/W Description
15
POE3F 0
R/(W)* POE3 Flag
This flag indicates that a high impedance request has
been input to the POE3 pin
Clear condition:
• By writing 0 to POE3F after reading a POE3F = 1
14
POE2F 0
Set condition:
• When the input set by ICSR1 bits 7 and 6 occurs
at the POE3 pin
R/(W)* POE2 Flag
This flag indicates that a high impedance request has
been input to the POE2 pin
Clear condition:
• By writing 0 to POE2F after reading a POE2F = 1
13
POE1F 0
Set condition:
• When the input set by ICSR1 bits 5 and 4 occurs
at the POE2 pin
R/(W)* POE1 Flag
This flag indicates that a high impedance request has
been input to the POE1 pin
Clear condition:
• By writing 0 to POE1F after reading a POE1F = 1
12
POE0F 0
Set condition:
• When the input set by ICSR1 bits 3 and 2 occurs
at the POE1 pin
R/(W)* POE0 Flag
This flag indicates that a high impedance request has
been input to the POE0 pin
Clear condition:
• By writing 0 to POE0F after reading a POE0F = 1
11 to 9 
All 0
Set condition:
• When the input set by ICSR1 bits 1 and 0 occurs
at the POE0 pin
R
Reserved
These bits are always read as 0s and should always
be written with 0s.
Rev. 2.0, 09/02, page 341 of 732