SH7144 Datasheet, PDF (468/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 14.6 The Relationship between Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/0 1/0 0
0
0
0
0
00
0
0
Idle condition
(flag must be cleared.)
1
1
0
0
0
0
0
00
0
0
Start-condition issuance
1
1
1
0
0
1
0
00
0
0
Start-condition satisfaction
1
1/0 1
0
0
0
0
00
0
1/0
Master-mode wait
1
1/0 1
0
0
1
0
00
0
1/0
End of master-mode
transmission/reception
0
0
1
0
0
0
1/0
1 1/0 1/0 0
Arbitration lost
0
0
1
0
0
0
0
01
0
0
SAR match in the first
frame of slave-mode
operation
0
0
1
0
0
0
0
01
1
0
General call address match
0
0
1
0
0
0
1
00
0
0
SARX match
0
1/0 1
0
0
0
0
00
0
1/0
End of slave-mode
transmission/reception
(other than for an SARX
match)
0
1/0 1
0
0
1
1
00
0
0
End of slave-mode
0
1
1
0
0
0
1
00
0
1
transmission/reception
(other than for an SARX
match)
0
1/0 0
1/0
1/0
0
0
00
0
1/0
Stop-condition detection
Rev. 2.0, 09/02, page 428 of 732