SH7144 Datasheet, PDF (758/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Item
Figure 11.50 Example
of Output Phase
Switching by External
Input (1) to Figure 1.53
Example of Output
Phase Switching by
Means of UF, VF, WF
Bit Settings (2)
Table 11.42 MTU
Interrupts
Page
281,
282
285
Figure 11.64 TGI
291
Interrupt Timing
(Compare Match)
Revisions (See Manual for Details)
Description amended.
When BCD = 1, N = 1, P = 1 ⋅⋅⋅⋅⋅⋅
→ When BDC = 1, N = 1, P = 1 ⋅⋅⋅⋅⋅⋅
Description added.
Channel Name
4
TCIV_4
Interrupt Source
TCIV_4 overflow/underflow
Figure amended.
Pφ
Compare
match signal
11.7.18 Cautions on 305
Transition from Normal
Operation or PWM
Mode 1 to Reset-
Synchronous PWM
Mode
11.7.21 Simultaneous
Capture of TCNT_1
and TCNT_2 in
Cascade Connection
Figure 11.85 Error
Occurrence in Normal
Mode, Recovery in
Normal Mode to Figure
11.113 Error
Occurrence in Reset-
Synchronous PWM
Mode, Recovery in
Reset-Synchronous
PWM Mode
Figure 11.115 Low-
Level Detection
Operation and Figure
11.116 Output-Level
Detection Operation
306
309 to
337
346
Description amended.
When making a transition from normal operation to reset-
synchronous PWM mode, write H'11 to registers TIORH_3,
TIORL_3, TIORH_4, and TIORL_4 to initialize the output
pins to low level output, then set an initial register value of
H'00 before making the mode transition.
Description changed.
Description amended.
MTU output → MTU module output
Symbol amended.
CK → Pφ
Rev. 2.0, 09/02, page 718 of 732