SH7144 Datasheet, PDF (525/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

16.3.2 CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ)
can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 16.3 shows the CMCNT count
timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
Figure 16.3 Count Timing
16.4 Interrupts
16.4.1 Interrupt Sources and DTC Activation
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when interrupt request
flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by means of interrupt controller settings. See section 6, Interrupt Controller, for details.
The data transfer controller (DTC) can be activated by an interrupt request. In this case, the
priority between channels is fixed. See section 8, Data Transfer Controller, for details.
16.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 16.4 shows
the CMF bit set timing.
Rev. 2.0, 09/02, page 485 of 732