SH7144 Datasheet, PDF (114/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Bit Bit Name Initial Value R/W Description
1
IRQ7ES1 0
0
IRQ7ES0 0
R/W This bit sets the IRQ7 interrupt request edge
R/W ^{detection mode.}
00: Interrupt request is detected on falling edge of
IRQ7 input
01: Interrupt request is detected on rising edge of
IRQ7 input
10: Interrupt request is detected on both of falling
and rising edge of IRQ7 input
11: Cannot be set
6.3.3 IRQ Status Register (ISR)
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
cleared by writing 0 to IRQnF after reading IRQnF = 1.
Bit
Bit Name Initial Value R/W
15 to 8 —
All 0
R
7
IRQ0F 0
R/W
6
IRQ1F 0
R/W
5
IRQ2F 0
R/W
4
IRQ3F 0
R/W
3
IRQ4F 0
R/W
2
IRQ5F 0
R/W
1
IRQ6F 0
R/W
0
IRQ7F 0
R/W
Description
Reserved bits
These bits are always read as 0. The write value
should always be 0.
IRQ0 to IRQ7 Flags
These bits display the IRQ0 to IRQ7 interrupt request
status.
[Setting condition]
• When interrupt source that is selected by ICR 1
and ICR2 has occurred.
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
• When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and
rising edge.
• When the DISEL bit of DTMR of DTC is 0, after
DTC has been started by IRQn interrupt.
Rev. 2.0, 09/02, page 74 of 732