SH7144 Datasheet, PDF (652/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

23.1.2 Block Diagram
Figure 23.1 shows a block diagram of the AUD.
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDMD
AUDCK
PC output circuit
Address buffer
Data buffer
Mode control
Bus
controller
Internal Peripheral
bus
module bus
On-chip
memory
CPU
On-chip
peripheral
module
Figure 23.1 AUD Block Diagram
23.2 Input/Output Pins
Table 23.1 shows the AUD's input/output pins.
Table 23.1 AUD Pin Configuration
Name
AUD data
AUD reset
AUD mode
AUD clock
AUD sync signal
Abbreviation
AUDATA3 to
AUDATA0
AUDRST
AUDMD
AUDCK
AUDSYNC
Function
Branch Trace Mode
RAM Monitor Mode
Branch destination address
output
Monitor address/data
input/output
AUD reset input
AUD reset input
Mode select input (L)
Mode select input (H)
Sync clock (φ/2) output
Sync clock input
Data start position
identification signal output
Data start position
identification signal input
Rev. 2.0, 09/02, page 612 of 732