SH7144 Datasheet, PDF (59/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 2.2 Sign Extension of Word Data
CPU of This LSI
Description
MOV.W
ADD
.DATA.W
@(disp,PC),R1 Data is sign-extended to 32
R1,R0
.........
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
H'1234
instruction.
Note: @(disp, PC) accesses the immediate data.
Example of Conventional CPU
ADD.W #H'1234,R0
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions.
With a delayed branch instruction, the branch is taken after execution of the instruction following
the delayed branch instruction. This reduces the disturbance of the pipeline control in case of
branch instructions. There are two types of conditional branch instructions: delayed branch
instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions
CPU of This LSI
BRA
TRGET
ADD
R1,R0
Description
Executes the ADD before
branching to TRGET.
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one to two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit
+ 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states.
T Bit: The T bit in the status register changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Rev. 2.0, 09/02, page 19 of 732