SH7144 Datasheet, PDF (43/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

1.2 Internal Block Diagram
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVcc
PLLCAP
PLLVss
FWP*
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
AVcc
AVss
DBGMD
P
L
L
;;;; _AUD*
Flash ROM/
mask ROM
256kB
RAM
8kB
;^;;^;;;; _CPU
;;^;;;^{;;; Interrupt Userbreak}
controller controller
Data transfer
Controller
Direct memory
access controller
Bus state
controller
Serial communication
interface
;; ( 4 channels)
Compare match
timer
( 2 channels)
Multifunction
timer pulse unit
A/D
Watchdog
converter timer
;;;;;;;;;;;_;; ^{I2C bus interface}
H-UDI*
PC15/A15
PC14/A14
PC13/A13
PC12/A12
PC11/A11
PC10/A10
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
PD15/D15/
PD14/D14/AUDCK
PD13/D13/AUDMD
PD12/D12/
PD11/D11/AUDATA3
PD10/D10/AUDATA2
PD9/D9/AUDATA1
PD8/D8/AUDATA0
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2
PD1/D1
PD0/D0
Peripheral address bus (12bits)
Peripheral data bus (16bits)
Internal address bus (32bits)
Internal upper data bus (16bits)
Internal lower data bus (16bits)
Note: Modules for the F-ZTAT reision only
Figure 1.1 Internal Block Diagram of SH7144
Rev. 2.0, 09/02, page 3 of 732