SH7144 Datasheet, PDF (266/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.3.6 Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
11.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3,
and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA and
TGRC and TGRB and TGRD.
The initial value of TGR is H′FFFF.
Rev. 2.0, 09/02, page 226 of 732