SH7144 Datasheet, PDF (339/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

11.7.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.77 shows the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 11.77 Contention between TGR Write and Input Capture
Rev. 2.0, 09/02, page 299 of 732