SH7144 Datasheet, PDF (162/773 Pages) Renesas Technology Corp – Hitachi SuperH RISC engine

Table 8.6 State Counts Needed for Execution State
Access Objective
On-chip On-chip Internal I/O
RAM ROM Register
Bus width
Access state
32
32
8 or 16
1
1
2*¹
3*²
Execution Vector read
S_I
—
state
Register information S
1
J
read/write
1
——
1
——
Byte data read
S_K
1
1
2
3
Word data read
S_K
1
1
2
3
Long word data read S_K
1
1
4
6
Byte data write
S_L
1
1
2
3
Word data write
S_L
1
1
2
3
Longword data write S_L
1
1
4
6
Internal operation
S_M
1
Notes: 1. Two state access module : port, INT, CMT, SCI, etc.
2. Three state access module : WDT, UBC, etc.
External Device
8
16 32
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Execution
state
count
=
I
·
S
I
+
Σ
(J
·
S
J
+
K
·
S
K
+
L
·
S)
L
+
M
·
S
M
8.4 Procedures for Using DTC
8.4.1 Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in
memory space.
2. Specify the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. The DTC is activated when an interrupt source occurs.
5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER
is not. When interrupts are requested, the interrupt source is not cleared, but the DTER is.
6. Interrupt sources are cleared within the CPU interrupt routine. When doing continuous DTC
data transfers, set the DTER to 1.
Rev. 2.0, 09/02, page 122 of 732